0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications

This paper presents a true random number generator utilizing the probabilistic delay of the cross-coupled latch during start up as an entropy source. The start-up signal is used as a slow and jittered clock to sample a fast ring oscillator to harvest random bit stream. The tunable jitter delay range and all-digital design ensure high quality random bits generation across a wide range of supply voltages. The test chip consumes 0.54 pJ/bit with a bit rate of 15Mb/s at 0.5 V supply voltage while occupying only 18% area of the state of the art. The design's compact area, simple interface, and high energy efficiency make it a well suited choice for edge computing applications.