Memory-Efficient Architecture for Contrast Enhancement and Integral Image Computation

This paper proposes a hardware architecture for contrast-limited adaptive histogram equalization (CLAHE) and integral image computation, focusing on the efficient use of memory resources. To save memory resources, the proposed architecture processes each pixel entered in real time without storing the entire image. In addition, this architecture improves resource utilization by optimizing the tile size of CLAHE and computing the integral image via an adder tree. When the proposed architecture was implemented in Xilinx's FPGA XC7Z045 FFG900-2, it used 98,945 slice LUTs, 85,600 slice registers, and 8 BRAMs for the CLAHE module, and it used 7,834 slice LUTs, 7,498 slice registers, and 19 BRAMs for the integral image module. In addition, the proposed architecture operated at a maximum frequency of 129 MHz in 512 × 512 image resolution.