FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation

This paper addresses efficient Field Programmable Gate Array (FPGA) implementations of radix-2 and radix-4 signed digit add-subtract architectures. The circuits have been realized by instantiating physical FPGA primitives and configuring them appropriately to obtain speed-area efficient realizations. Underutilized, yet configured logic primitives are targeted to reduce logic levels for certain implementations or append fault detection logic, such as alternating logic through self dual duplication, using a design automation framework. Simple C programs with linear computational complexity carries out the automation. Our proposed implementation outperforms architectures synthesized through behavioral modeling, or original architectures appended with state-of-the-art FPGA centric error-detection strategies, both in speed and area.