InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing

Low InP/dielectric interface trap density $D_{\mathrm{it}}$ will enable low subthreshold swings $(SS)$ in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing $D_{\mathrm{it}}$ at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract $D_{\mathrm{it}}$ of III-V interfaces from MOSCAP characteristics, $D_{\mathrm{it}}$ can be readily determined from the $SS$ of long gate length $L_{\mathrm{g}}$ MOSFETs. Here we report InP-channel MOSFETs with record low $SS$ indicating record low $D_{\mathrm{it}}$ at the semiconductor-dielectric interface. The devices use an AlOxNy/ZrO2gate dielectric and a 14nm channel thickness $T_{\mathrm{ch}}$. A sample of 13 MOSFETs at $2\ \mu \mathrm{m}L_{\mathrm{g}}$ shows $SS=70\mathrm{mV}/\mathrm{dec}$. (mean) $\pm 3\mathrm{mV}/\mathrm{dec}$. (standard deviation), corresponding to a minimum $D_{\mathrm{it}}\sim 3\times 10^{12}\mathrm{cm}^{-2}\mathrm{eV}^{-1}$. The lowest $SS$ observed at $2\ \mu \mathrm{m}L_{\mathrm{g}}$ is 66mV/ dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects.