Designing of Standard Cell Library for GBONOR Approach

Ground bounce noise reduction (GBONOR) approach is a transistor level ground bounce noise (GBN) reduction power gating technique. Power gating technique is used for reducing the leakage power in standby mode of the logic circuits by inserting the high threshold sleep transistors as a footer or header. Large instantaneous current is flowing in power gating structure during the mode transition that causes GBN on real ground rail. Logic states are deviated because of GBN. GBONOR is not only reduces the ground bounce noise but also mitigates leakage power in both operating modes. In this article, a minimum set of standard cells for GBONOR approach is generated. The standard cell library (SCL) contributed the basic gates at 32nm CMOS technology node. Silvaco's EDA tools are used for generation of SCL at nominal temperature and supply voltage of 0.8V. The cell height of all cells is fixed, and it is 1.58?m. 74181 circuit is designed and verified with GBONOR standard cells at transistor level design. GBONOR SCL saves 42.66% leakage power and improves GBN by 84.03% for 74181 circuit.