Area-Driven Architecture Oriented Resynthesis Algorithms for FPGAs

The majority of modern FPGA architectures are supposed to have some design solutions that allow to optimize digital circuits designs in terms of area and performance. In previous works, architecturally oriented area-driven resynthesis algorithms for generalized FPGA logic cell models were proposed. We propose two additional resynthesis algorithms in this work. First algorithm uses two independent cell's outputs to combine unconnected elements in a one cell. Second algorithm uses cell's built-in feedback interconnection to reduce total amount. The algorithms were tested on a set of logic synthesis benchmarks (IWLS-2005). For the first algorithm, the results show an occupied area reduction up to 5% compared with the results of previous work, that brings the total area reduction up to 39%. The second algorithm gains up to 11% reduction of the number of pin-to-pin design interconnections.