Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays

The emerging mobile devices in the era of Internet-of-Things (IoT) require a dedicated processor to enable computationally intensive applications such as neuromorphic computing and signal processing. Vector-by-matrix multiplication is the most prominent operation in these applications. Therefore, there is a critical need for compact and ultralow-power vector-by-matrix multiplier (VMM) blocks to perform resource-intensive low-to-moderate precision computations. To this end, in this article, we propose a time-domain mixed-signal VMM exploiting a modified configuration of 1MOSFET-1RRAM (1T-1R) array. The proposed VMM overcomes the energy inefficiency of the current-mode VMM approaches based on RRAMs. A rigorous analysis of different nonideal factors affecting the computational precision indicates that the nonnegligible minimum cell currents, channel length modulation (CLM), and drain-induced barrier lowering (DIBL) are the dominant mechanisms degrading the precision of the proposed VMM. We also show that there exists a tradeoff between the computational precision, dynamic range, and the area- and energy-efficiency of the proposed VMM approach. Therefore, we provide the necessary design guidelines for optimizing the performance. Our preliminary results indicate that an effective computational precision of 6 bits is achievable owing to the inherent compensation effect in the modified 1T-1R blocks. Furthermore, a 4-bit 200 × 200 VMM utilizing the proposed approach exhibits a significantly high energy efficiency of ~1.5 Pops/J and a throughput of 2.5 Tops/s including the contribution from the input/output (I/O) circuitry.