Design of Low-Voltage and Low-Power FGMOS Based Third Generation Current Conveyor in 90nm Regime and Application

We present a designed technique for third generation current conveyor(CC-III) and its application which is based on floating gate MOSFET (FGMOS). The design is simulated on 90nm cadence Virtuoso with 1.0V of Supply voltage. The purpose of this design is to minimize power dissipation and noise in the circuit which results in nano-scale circuit. The paper also presents the comparison results between CC-III based on Complementary MOSFET (CMOS) and FGMOS.