Linearity and Intermodulation Distortion Assessment of Underlap Engineered Cylindrical Junctionless Surrounding Gate MOSFET for Low Noise CMOS RFIC Design

In this paper the reliability of Junctionless Surrounding Gate MOSFET has been examined by investigating the effect of underlap engineering on the linearity and intermodulation distortions in order accredit the device efficacy for Low Noise SOC design for wireless applications. Linearity metrics namely V_IP3, g_m3, I_MD3, V_IP2, I_IP3 and 1 dB compression point have been studied for CJLSG MOSFET with and without gate underlap engineering (for different underlap lengths). Improvement in linearity metrics shows the appropriateness of the device for low distortion applications which further facilitates high scale integration. In addition to linearity noise metrics namely Noise Figure (NF) and Noise Conductance (NC) have also been analyzed for low noise applications.