Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS

This paper presents compensation circuit design for four-level pulse amplitude modulation (PAM4) transmitters with feed forward equalizing (FFE) in data transmission systems. The signal amplitude in PAM4 is small, particularly when the supply voltage is low. This leads to signal degradation. To maintain signal quality in PAM4 transmitters, we developed a design that performed within the appropriate combiner parameters. We conducted a post-layout simulation in an 180-nm CMOS process to confirm the advantage of the circuit. The rising and falling times were reduced by 7.4% and 2.4% compared with those of a conventional circuit.