The Crosstalk Analysis of FPGA High-Speed Signals with Generic Pre-layout Modeling

The crosstalk analysis of FPGA high-speed signals with generic pre-layout modelling approach effectively identify critical and dominant parameters for further optimizations to meet the channels timing without the need of having the completed design in place. Results show that the channel noise obtained from the pre-layout model correlates well with post-layout model simulation result, with up to 10GHz signal bandwidth. This approach also reduces the design cycle time from 3 days to 0.5 days, hence reducing the lead time in overall crosstalk analysis.