Simulation of Wire Bond Clamping and Its effect on Die Pad Tilt

Clamping is an important mechanism in the assembly process for semiconductor packaging. The leadframe which acts as a skeletal support for the package has to be clamped in every process starting from die attach to the final package singulation. Proper clamping of the package enables a smooth assembly process as well as ensuring the package reliability. However, it is always a challenge to define proper or sufficient clamping. Simulation on clamping mechanism using finite element analysis, such as tension testing machine, has been proven effective in analyzing and optimizing the clamping tools. A similar approach is used in this study to investigate the effect of unbalance clamping during wire bond process on die pad tilt. Die pad tilt is undesirable especially for exposed pad packages during molding process as it can potentially result in severe mold flashes at the exposed pad or leads. Unbalance clamping during wire bonding occurs due to many reasons. For instance, only one side of the die pad is clamped and the other side is not or one side of the die pad experience higher clamping force than the other side. 3-D finite element analysis was carried out on different clamp configuration with the same clamp tool design and package. Actual clamping was also conducted experimentally to verify the simulation results. Simulation results show a good correlation with actual clamping measurement where unbalance clamping configuration causes die pad tilt. The die pad tilt is a caused by high one sided clamping force resulting in plastic deformation on the leadframe which is not fully recoverable after the clamp is removed. The finite element approach provides a good understanding on the mechanism of clamping during wire bonding. It is also economical in terms of effort and time compared to actual experiment setup which is tedious and time consuming. Although the finite element method is only used as an investigation method in this study but it can also be utilized for clamp tool optimization especially the packages in semiconductor are increasingly more complicated than they were in the last decade.