Design of an FPGA/SoC Hardware Accelerator for MIT Coffee Can Radar Systems

For an autonomous vehicle running at highway speeds, processing and response time of radar sensors are of extreme importance. In this paper, we present hardware accelerators for MIT Coffee Can Radar systems [1] using commercial off-the-shelf FPGA/SoC boards [5], [6]. There are multiple advantages of this proposed system architecture, but the ability to process/average more chirp cycles without slowing down the radar sensor output rate is probably the most important one. Averaging over multiple chirps is a known technique which can be used to reduce measurement errors, suppress noise, and improve multi-target detection performance. However, to be able to do more averaging without slowing down the radar sensor output rate, the frequency of the ramp signal driving the VCO must be increased. This will result increased frequency IF signals, and hence will require faster ADC converters. On a multitasking system, this will also increase the size of the data transferred between kernel and user spaces, and will also require handling/averaging over larger arrays stored in the dynamic RAM. These are all known performance bottlenecks both for delay as well as for throughput [7]. We propose the use of a Zynq SoC based system for implementing the signal processing chain. Basically, there will be an application specific hardware accelerator which does averaging of the received signal over multiple chirps inside the FPGA fabric using static block RAMs with deterministic timing. This greatly reduces the computational load on the ARM side of the Zynq, and AXI bus data traffic. Overall, the proposed system will have reduced delays, improved performance, and better real-time characteristics. A preliminary version of the hardware accelerator is synthesized for an entry level Zynq board [5] for I MSPS ADC speed, 100MHz AXI bus speed, and without any pipelining technique. Total resource usage on the FPGA fabric was less than 10%, worst setup slack was 1.090 ns, and worst hold slack was 0.088 ns. All of these show the feasibility of the proposed proposed hardware accelerator.