UVM-based Logic Verification of Input Output Interface

Verification plays a very important role in the flow of chip design and fabrication. If a System-on-Chip (SoC) has many blocks within it, then verification must be first carried out at the block level and later at the full chip level. This paper presents a block level verification of a subsystem called Input Output Interface. A constrained random testbench is developed using the standard Universal Verification Methodology (UVM) architecture. UVM has been used to create a reusable testbench. The created testbench is used to run multiple tests so as to cover all parts of the design. The goal of this verification process is to obtain hundred percent code coverage and functional coverage. Many features of System Verilog (SV) such as assertions, coverpoints and covergroups, multithreading have been incorporated into the testbench.