A 80∼101GHz Amplifier in 65nm CMOS process

This paper presents an 80~101 GHz low-noise amplifier (LNA) with 65-nm CMOS process. The first stage of the proposed low noise amplifier employs a novel amplifier structure to improve the noise figure and gain, which consists of a cascode amplifier and a feedback loop. The other stages are employed the cascode amplifier with gain improvement technique to improve the gain. The simulation results show that the LNA can provide a gain of 17 dB with a 3 dB bandwidth of 21 GHz. With 1.2-V power supply, the LNA consumes 24-mW power consumption. Furthermore, the LNA achieves minimum noise figure (NF) of 6.5 dB at 90 GHz and NF of 6.5~8.0 dB within a 3 dB gain bandwidth.