A Novel Data Packing Technique for QC-LDPC Decoder Architecture applied to NAND flash controller

This paper presents a data packing technique for Quasi-Cyclic LDPC codes decoder applied to NAND flash controller which has the challenge of long code length implementation due to high complexity and routing congestion on floor planning. Firstly, we introduce a proposed shift network to reorder the channel data sequence. The data packing mechanism is designed to be generic. Secondly, the proposed LDPC architecture is desgined to overcome complicated routing problems caused by random accessing of massage passing within the LDPC decoder. Based on the proposed architecture, the hardware description has been synthesized on Design Compiler using a TSMC 0.18um model and an FPGA-based floor planning with the implementing result has also been provided. Synthesis results also show that the area and throughput of the proposed decoder has desirable performance for the application of NAND flash controller.