Light Weight and Fast Simulation Methodology in SystemC for TLM based Behavior Modeling of Programmable Processors

Behavior model of processor cores helps in the performance evaluation of applications and design space exploration of processor architectures such as DSPs, AI processors, etc. even before they are taped out. SystemC is a widely used modeling language to model such processor architectures. High simulation speed of these models are essential for fast evaluation of architectures with application benchmarking and also to meet time-to-market of processor design. However, the traditional SystemC based processes such as SC_CTHREAD, SC_THREAD, and SC_METHOD are limiting the simulation speed due to their frequent context switches, complex event handling and generic nature to cater all types of simulation requirements of EDA industry. In this paper, we propose a novel simulation methodology in SystemC with a new process SC_LIGHT_PROCESS and an ultra light weight simulation engine to achieve 2.6× to >7.9× simulation speed compared to recent SystemC modeling methodologies. Our approach is best suited for easy behavioral modeling of processor architectures in SystemC and requires neither event queues nor complex scheduler. It has been evaluated with behavioral modeling of Audio/Video DSP Reconfigurable Processor system for wide range of audio/video applications.