A Reconfigurable CNN Accelerator using Tile-by-Tile Computing and Dynamic Adaptive Data Truncation

This paper proposed a Reconfigurable Neural Accelerator (RNA) for multiple CNNs acceleration. A novel tile-by-tile computing (TTC) model is designed for RNA to fully reuse data between convolutional layers and significantly decrease data transmission, which can substantially reduce memory bandwidth requirement and improve throughput. Besides, an on-line dynamic adaptive data truncation (DADT) mechanism is designed to activate the intermediate result data generated by multiplier, which can compensate accuracy loss from fixed-point operation in RNA. The RNA architecture was implemented on Xilinx XC7VX485 FPGA and working at 200 MHz. Testing results show that the performance of running LeNet, AlexNet and VGG are 400 GOPS, 498 GOPS and 528 GOPS, respectively. The average energy efficiency of RNA is 71.7 GOPS/W at 6.63 W power consumption.