10-bit 47.57μW Power Efficient Successive Approximation Register ADC with High Speed

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) prototype is presented in this work and simulations are performed using Cadence Spectre on 16 nm technology. This architecture consists of a bulk driven rail to rail comparator and split binary weighted capacitive Digital to Analog Converter (DAC). Both comparator and DAC are significant part of Analog to Digital Converter (ADC) which helps to achieve high speed with less power consumption and improved linearity. The power consumption is 47.57 μW. The Spurious Free Dynamic Range (SFDR) and Signal to Noise plus Distortion Ratio (SNDR) are 68 dB and 63 dB, respectively. The proposed design operates with 100 MSps speed while the comparator and Successive Approximation Register (SAR) control logic operates at 1GHz.