FPGA implementation of exponential function using cordic IP core for extended input range

This paper proposes a method and a hardware architecture to calculate the exponential value of an input outside the convergence range of CORDIC IP core in FPGAs. Exponential function is an incremental function which finds extensive applications in the area of signal processing and communication. In applications where speed is of utmost importance hardware implementation of unary functions like sine, cosine and exponential becomes crucial. CORDIC algorithm can be used to find exp function but its input range is limited to [-1.12, +1.12]. The method described in this paper can be used to find exponential values of large inputs, both positive and negative. CORDIC IP core available in FPGA is used in this design but it can also be used with conventional cordic algorithm. This digital design was simulated with fixed point (32-bit word length,16-bit fractional point) numbers in Xilinx ISE and synthesized for Xilinx Spartan- 6 FPGA. The range of input was extended to [-9.5,+9.5].