Low Power Single Bit-line Power-gated SRAM

A system-on-chip contains various components of which memory is one of the prominent block. As the technology is growing and portable devices are taking charge of all our digital activities, it becomes important that these devices consume less power and still give optimum performance. In this paper, a low power and low leakage power consuming single bit-line SRAM has been designed. It provides a high value of static noise margin during read function with good static as well as dynamic write and read performance. Multi-threshold sleep transistors are used to reduce leakage power in the designed SRAM. The usage of sleep transistors provides low leakage power in the SRAM circuit. Due to this, the leakage power reduces by 23.33% when compared with the 9T single bit-line circuit. In order to further reduce leakage power and circuit performance, power-gating method is applied to the SB9T circuit. It is observed that this method yields better access times and stability of the circuit. The hold and read SNM improve and the values are close to each other. The leakage power reduces by 63.9% due to this method. The performance parameters of SB9T, Sleepy SB9T and PG-SRAM are compared. It is found that the power-gated circuit performs most efficiently among the three designs. A 2×2 array for the SB9T and the PG-SRAM are designed in this paper and it's found that the leakage power consumed is 14.58% less in the power gated array compared to the normal SRAM.