Performance Analysis of Integrated ADC & DAC with PLL for future communication systems

The main constraints in the current communication scenario is the requirement of high speed Analog to Digital Converter's & Digital to Analog Converter's with the low power, area & cost implementation with acceptable performance measures. The current trends of transceivers are designed based on the stand alone ADC & DAC with the clock given externally. In this paper, the comparison between the stand alone ADC & DAC with the integrated ADC & DAC with Phase Locked Loop is carried out. The hardware implementation is made with the IC's interfaced to FPGA. The characterization is carried out with respect to the utilization of integrated ADC & DAC in the Small cells for Long Term Evolution communication. The LTE Time Division Duplex bands are generated & captured using standalone ADC & DAC and integrated ADC & DAC with PLL. The results show that the integrated ADC performance over LTE TDD bands is degraded in terms of SNR by 12.61%, Spurious Free Dynamic Range by 13.40% and integrated DAC performance is degraded in terms of SNR by 11.97%, SFDR by 12.96%. From the results, it is evident that the performance variation is less than 15%, which will be the trade-off when using integrated ADC & DAC with PLL for low power, cost & area implementations.