Design and Analysis of Low Power, High Speed 4 - Bit Magnitude Comparator

This paper illustrates the design of low power, high speed 4 Bit Magnitude Comparator. The NOR gate logic used in this paper to design the proposed circuit can help in designing of low power, high-speed larger N-bit magnitude comparators. The performance is analyzed for the proposed comparator design for power consumption, delay & Power-delay Product (PDP) with Vdd Sweep. The design and simulation are done on Cadence Virtuoso Tool Using 180nm CMOS Technology. The simulation results of proposed comparator circuit are in good agreement in terms of power consumption at the percentage of 31.77% and power delay product at the percentage of 35.39%. The Layout is also designed for Proposed Comparator. The proposed circuit is using less number of MOSFETs as compared to Basic Conventional Circuit. This will further reduce the area of the chip, which is currently the most important task in the VLSI industry.