Impact on the Physical Design flow, due to Repositioning the Macros in the Floorplan stage of Video decoder at Lower Technologies

As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe challenges of Timing, Run time, Congestion, QOR, Yield & manufacturing limitations. In this paper, mostly discuss on how macro placing in floorplan affect Timing, Congestion, QOR, DRC's of every stage in the design flow. Two test cases are considered to compare their congestion, utilization ratio, QOR, DRC's and finding out which macro placings is efficient for design requirement.