Functional Read Enabling In-Memory Computations in 1Transistor—1Resistor Memory Arrays

`In-memory computing' is an emerging paradigm that attempts to embed some aspects of logic computations inside memory arrays leading to higher throughput and lesser energy-consumption. Consequently, various in-memory compute proposals using emerging non-volatile technologies based on functional read- wherein multiple word-lines are simultaneously activated and a Boolean function of the constituent activated rows is read, is being extensively investigated. In this brief, we first show that the conventional sensing scheme for such functional reads, operated on 1 Transistor - 1 Resistor (1T-1R) memory arrays, is limited theoretically by low sense-margin. We demonstrate that the sense-margin does not improve even if the ON-OFF resistance difference is increased from low values to considerably higher values. Subsequently, we present a new sensing scheme based on skewed sense-amplifiers and staggered world-line activation as a method for enabling functional read operations. We show that in-memory XOR, IMP (implication) and bit-wise comparison can be easily implemented through the proposed scheme.