Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Excess source and drain (S/D) recess depth (TSD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I
_off
, I
_on
) in three-stacked NS channels and parasitic bottom transistor (tr
_pbt
), gate capacitance (C
_gg
), intrinsic switching delay time (τ
_d
), and static power dissipation (P
_static
) are investigated quantitatively according to the T
_SD
variations. More S/D dopants diffuse into the tr
_pbt
with the deeper T
_SD
, so the I
_off
and I
_on
increase due to raised current flowing through the tr
_pbt
. Especially, the I
_off
of PFETs remarkably increases above the certain T
_SD
(T
_SD,critical
) compared to NFETs. Furthermore, the Ion contribution of each channels having the T
_SD,critical
is the largest at the top NS channel and the tr
_pbt
has the ignorable I
_on
contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) I
_on
contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C
_gg
also increases with the deeper T
_SD
by increasing parasitic capacitance, but fortunately, the τ
_d
decreases simultaneously due to the larger increasing rate of the Ion than that of the C
_gg
for all SoC applications. However, the P
_static
enormously increases with the deeper T
_SD
, and low power application is the most sensitive to the T
_SD
variations among the SoC applications. Comprehensive analysis of the inevitable tr
_pbt
effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.