FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection

In this paper, we present a Field Programmable Gate Array (FPGA) based design for suppression of high frequency noise and detection of seismic events in a fast-arriving P-wave for the development of an early earthquake warning system. The key motivation of this research was to design an accelerated hardware platform to reduce the response time of the early warning system. It consists of two types of FIR filter: low pass FIR filter and another moving average filter (short term and long term). We explore three different architectures for the FIR low pass filter in order to optimize delay and area. The ratio of the short term averaging and long term averaging is compared with a pre-defined threshold level to detect seismic event. The entire design is implemented in Xilinx Vivado 2015.4 platform targeted towards ZED board. The design is validated through carefully generated seismic signals.