Process Corner Calibration for Standard Cell Based Flash ADC

This paper proposes a self-calibration technique for process corner variations on standard cell based flash ADC. Standard cell based ADCs undergoes a drastic variation in the switching threshold of each comparators during fabrication at different process corner. This demands for stringent process calibration technique at all the corners. This work fulfills the requirement and reduces the process variations to a great extent. The architecture is designed and simulated using a 180 nm CMOS technology for 5-bit standard cell based Flash ADC with a supply voltage of 1.8 V. The results show that the effective number of bits (ENOB) of 4.5 bits has been achieved after the calibration, when compared to the ENOB of 3.1 bits without calibration. The proposed calibration technique has a power consumption of 1.8 mW, which is 11% of the total power consumption without calibration.