Low Power Hardware Based Real Time Music System and Digital Data Transmission Using FPGA

This paper presents implementation of FPGA based low power music system and digital data transmission in real time environment. The proposed system consists of a music source, voltage divider, JXADC Pmod, Artix-7 Processor, DDR2 memory and Mono Audio Out. Music source provides analog input using auxiliary wire to the JXADC port. The music data is sampled at 44.1 KHz using JXADC and output is taken from the headphone jack using PWM. JXADC port requires bias voltage of 0.5volt, which is made available from on-board 1volt rail found on J14. A divider circuit is used to obtain 0.5volt out of 1.0volt input. Nexys4 DDR board is used for designing the algorithm of real time music system. Algorithm is designed using Verilog on Vivado 2018.3 Design Suite. In this process XADCs consume 0.002W out of the total power 1.198W. The music system provides an excellent music data to the audio out pin J8 in real time.