Design and Implementation of Vinculum Binary Coded Decimal Multipliers using Vinculum Binary Coded Decimal Compressors

Compressor logics are used to speed up the processing time. These structures are used for addition of Partial Products in multipliers. It reduces the complexity by reducing number of stages in addition. This paper speaks about addition of partial products using Vinculum BCD compressors under Vedic Mathematics. The proposed architecture reduces 7.04% of delay over VBCD and around 20% delay on conventional BCD multipliers when it was synthesized and simulated on vertex 6 platform using Xilinx 14.2i.