Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD

In this work generating test pattern using zero suppressed binary decision diagram (ZBDD) to generate test patterns for combinational circuit has been used. The ZBDD for combinational circuits are first obtained then test patterns are generated from it, similar approach is used for fault injected ZBDD and XOR operation is performed of both the set of test patterns to generate test pattern to detect the fault. This approach will reduce the power consumption during test mode of a circuit.