Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture

Secure encryption algorithms with advanced key executive techniques constantly help to achieve privacy, verification, and security of the data and curtail the overheads of the system. Currently, the prominent cryptographic technique is the Advance Encryption Standard (AES). The 128-bit pipelined cipher AES components adopt the symmetric-block cipher algorithm for encryption of the data. Our application achieves a high-level of encryption of 25.6 Gbps with an effective inter-and-intra-round layout. This module is designed on Xilinx ISE® Design Suite 14.7 and optimized for faster conversion speeds as the module is based on the pipeline architecture to perform the repeated array of operations known as the round. The designed module is suitable for high-security data communication, image processing, and other embedded applications. Pipelined architecture reduces the time associated with each encryption process and decreases the total time it takes for a plaintext block to encrypt.