Implementation Of Graph Based Clustering For Real Time Image Analysis

Clustering is used in image analysis to group or segment the image. This paper presents the VLSI architecture for clustering based on graph partition technique using FPGA. The balanced graph is built using KD tree. The architecture uses an indexing technique that reduces the memory overhead in multi-dimensional data. The architecture is tested for its working using Xilinx/ISim tool and the design is implemented using FPGA Virtex 6. By varying the number of inputs that can be processed, the hardware cost is analyzed. Due to parallel computations, the proposed architecture has a throughput of 40-50fps.