An Ultra Low Power VLSI Architecture for Viterbi Decoder using Subthreshold Adiabatic Logic

In modern digital world, the major features expected are portability and reliability. There is a tremendous development in the field of wireless communication systems. Viterbi decoder, the heart of the wireless communication receivers, facilitates the correction of transmission errors occurred in the transmission channels. To realize a portable system, ultra low power digital integrated circuit design is vital. In this paper, we reduced the power consumption of Viterbi decoder and thereby reduced the heat dissipation of the integrated circuits. We propose a novel technique, Viterbi decoder based on sub-threshold adiabatic logic, to achieve power reduction. This approach is used where power consumption is the major concern instead of performance. It is observed that the power consumption of the circuits is more desirable compared with conventional static CMOS implementation.