A Novel Ternary Half Adder & One Bit MultiplierCircuits based on Emerging sub-32nm FET Technology

In this paper, we present a novel low-power and high-performance new ternary logic arithmetic circuit that is implemented by double gate (DG) FinFET and graphenenanoribbon (GNR) field effect transistor (GNRFET). Multiple-valued logic (MVL) such as penternary, quaternary and ternary is a promising alternative to the binary logic design, because of less complexity, less computational step and reducedchiparea. The basic ternary gates and its operation are already described in my previous paper [20]. Ternary logic gate based arithmetic combinational circuits such as ternary half adder and one-bitternary multiplier are designed. The proposed ternary combinational circuits are simulated using HSPICE via standard 32nm DG-FinFET and GNRFET technology. Extensive simulation results demonstrate that the Graphene field effect transistor based ternary logic arithmetic circuits are more improved than the DG FinFET technology in terms of power consumption, delay and Power delay product (PDP).