A Deep Neural Network Accelerator Based on Tiled RRAM Architecture

State-of-the-art deep neural networks (DNNs) have been successfully mapped on an RRAM-based tiled in-memory computing (IMC) architecture. Effects of moderate array size and quantized partial products (PPs) due to ADC precision constraints have been analyzed. Methods were developed to solve these challenges and preserve DNN accuracies and IMC performance gains in the tiled architecture. Popular models including VGG-16 and MobileNet have been successfully implemented and tested on ImageNet dataset.