Area-Selective-CVD Technology Enabled Top-Gated and Scalable 2D-Heterojunction Transistors with Dynamically Tunable Schottky Barrier

2D semiconductors have emerged as attractive channel materials for ultra-short-channel field-effect transistor (FET) application, because of their atomic-scale thickness and pristine surfaces that effectively suppress short-channel effects. However, large contact and series resistances induced by Fermi-level pinning effect between metals and most 2D semiconductors (2DS) and the lack of an effective and reliable doping technique for the 2D source/drain, respectively, are limiting the performance of 2D-FETs. Moreover, wafer-scale synthesis of uniform and high-quality 2DS is a persistent challenge. In this work, we address all these challenges by demonstrating the advantages of replacing 2DS with work-function tunable and semi-metallic graphene (Gr) in the source/drain regions of 2D FETs, i.e., forming Gr-2DS-Gr lateral heterojunction FETs (GSG-HFETs), in terms of reducing the contact and series resistances. GSG-HFETs of various sizes are successfully fabricated, using area-selective CVD, thereby bypassing the need to synthesize wafer-scale 2DS. Based on meticulous device design and optimization, record-high ON-current (273 μA/μm) and ultralow contact resistance (~0.67 kΩ·μm) are achieved in a monolayer 2DS. Additionally, non-equilibrium Green's function (NEGF) based ballistic quantum transport simulation study on the scalability and upper-limit of the performance of this novel device uncovers its great potential in driving 2D-FETs toward nanometer scale and large-scale production.