Strain and surface orientation engineering in extremely-thin body Ge and SiGe-on-insulator MOSFETs fabricated by Ge condensation

We propose and demonstrate a new channel strain control technology enabling to realize both high performance tensile strain Ge-on-insulator (GOI) n-MOSFETs and compressive strain GOI p-MOSFETs on a same substrate. It is found that additional oxidation at 850 ^oC after Ge condensation changes the strain condition in GOI from 1.8 % compressive strain to 0.5% tensile strain, resulting in the electron mobility enhancement of 2.1. Furthermore, thinning GOI channel thickness introduces significant mobility enhancement attributable to GOI band modulation, leading to electron mobility of 777 cm²/Vs in n-MOSFETs with GOI thickness of 2.5 nm. For performance enhancement of p-MOSFETs, (110)-oriented SGOI formation by Ge condensation is studied. It is found that SGOI with the Ge fraction of 54 % maximizes the hole mobility from the viewpoints of both strain and Ge fractions. Record high hole mobility of 837 cm²/Vs is demonstrated with compressive strain (110) 27-nm-thick Si0 46G0 54OI p-MOSFETs, compared with mobility in planar GOI/SGOI p-MOSFETs reported so far. In addition, high hole mobility of 295 cm²/Vs is still maintained for 5-nm-thick extremely-thin body (110) Si0 46G0 54OI p-MOSFETs.