Performance Improvement of Region-Based Fault-Tolerant Routing Methods Based on the Passage of Fault Blocks

Toward the realization of dependable high-end consumer electronics products, a fault-tolerant 2D mesh Network-on-Chips (NoCs) in many core processors has attracted attention. In the previous method, we proposed a new approach to improve performance of a fault-tolerant routing method; packets can pass through faulty elements. In the study, we propose a new fault-tolerant routing method applying the new approach to a fault-tolerant routing method, which exhibits capable of high resource usage rate. This study investigates effect of the approach in reducing network congestion in the NoC. Simulation result shows that our method reduces average communication latency by about 62.8%, compared with our previous method.