Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET

The statistical variability in nano-scaled devices due to line-edge roughness (LER) is a major challenge for further scaling of device dimensions in multi-gate FETs. The LER in Double-Gate (DG) MOSFET is mainly due to silicon body thickness fluctuations (BTF) and oxide thickness fluctuations (OTF) along the channel direction. The effect of variation of channel length along the width direction (gate LER) is negligible in this device. In this paper, the threshold voltage (V
_TH
) fluctuations due to BTF and OTF in 30-nm DG MOSFET are analyzed for various device parameters and supply voltage through TCAD simulations. The devices with intrinsic channel and shorter gate length are found to have larger threshold voltage fluctuations due to LER.