Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN

Spiking CNN can greatly reduce the computation and accordingly reduces the energy consumption with a small penalty to the accuracy, but the network latency is significantly increased because of the long spike trains. In this paper, we first introduce layer factors in the normalization of the synaptic weights and propose a greedy method to search proper layer factors for improving the network latency. Second, we present a customizable CMOS/ReRAM hybrid hardware architecture for Spiking CNN. The architecture consists of an array of configurable basic units (CBU), which involves a CMOS adder for neuron operations and a 1T1R memristive crossbar for storing synaptic weights. A column of CBUs can be configured as spiking neurons corresponding to convolutional kernels with various sizes while the whole array can be configured to provide row parallelism for a kernel convolution and inter-kernel parallelism. The input spike trains are transmitted between CBUs and are reused by different spike neurons when performing parallel computing of rows in spike feature maps. The results show that the network latency can be reduced 42.3% for an accuracy of 98.04% in LeNet-5 by introducing layer factors. To our best knowledge, this is the first work to design customizable hardware architecture for Spiking CNNs. The simulation results show that the Spiking CNN consumes only 15.4% of the energy consumption of PipeLayer when processing the MNIST dataset.