A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period

A 10b SAR ADC which can be used as the last stage in a high-speed and high-resolution pipelined-SAR ADC is proposed. With the presented high-speed SAR logic, more than half of time in a sampling period is unused, which is a benefit for other stages in pipelined-SAR ADC with tighter timing. A unit capacitor with low parasitic effect is also presented. Together with redundancy and carefully placement in layout, the linearity of CDAC is improved. The noise of high-speed comparator is decreased because of the enlarged size in the input MOSFETs. The prototype ADC is implemented in UMC 28nm process. At 250MS/s and 1.05V supply, the ADC consumes 3.23mW and achieves 9.34b ENOB with an SFDR of 79.9 dB and an SNDR of 58.0 dB. The FoMw is 22.46 fJ/conv.step.