A New Twiddle Factor Merging Method for Low Complexity and High Speed FFT Architecture

FFT is one of the most widely-used algorithms in signal processing and communications applications. Although its realization in hardware-efficient FFT designs has been studied, there is still room to further reduce the complexity of FFT architectures by exploring more efficient expressions of twiddle factors in FFT. In this paper, a new 16-point FFT architecture is designed. A twiddle factor merging method is proposed to reduce the number of multiplications, additions and subtractions used in the design. To further improve the design, we apply a common subexpression sharing scheme to optimize the hardware resource sharing among the twiddle factors. Compared with previously published method, the proposed 16-point FFT architecture gains 25.4% and 14% improvement on hardware cost and delay respectively.