Multiplier Using NAND Based Compressors

In this paper, NAND based 5:3 compressor is proposed and is used to implement a high order 15:4 compressor. The 15:4 compressor's performance that uses proposed 5:3 compressor is compared with the implemented 15:4 compressor using existing low order compressors such as 6:3, 7:3 & using full/half adders. Compressors are used to add the partial product terms in the multiplier design at various stages. All the low order compressors use stacking approach to minimize the number of XOR gates along the critical path that uses basic logic gates for implementation. As per the proposed idea all the low order compressors are designed using only NAND gates for the comparison purpose and are in turn used to implement high order 15:4 compressor. Usage of NAND gates only in the design improves the design uniformity and gives better comparison in terms of the delay through the critical path. The optimum result for area, power and delay is observed for the 15:4 compressor implemented using 5:3 compressor proposed in this paper. This optimized 15:4 compressor as a major block of high order compressor, along with required number of other low order compressors, is used to implement a 16×16 multiplier and compared with existing 16×16 Wallace tree multiplier explained in literature survey. The functional simulation is carried out using Xilinx and the performance comparison is done using Cadence RTL compiler at 90 nm technology. The result shows that there is an improvement of 6.01%, 4.243%, & 9.97% with respect to area, power & delay respectively, in 16×16 multiplier using proposed idea when compared with existing 16×16 Wallace tree multiplier.