Design of FPGA based phase reconfiguration technique

Synchronization is an important parameter for the validity of data in the high energy physics experiments. There are numerous sources of uncertainties in the large experiments like Large Hadron Collider. This disrupts the phase alignment between the clocks and corrupts the data. In this paper we have proposed a FPGA based phase reconfiguration technique and implemented on Intel Stratix-V FPGA. The technique monitors the phase difference of the order of nanoseconds between the clocks and recovers the data alignment. The study is focussed on the implementation and testing of the technique for rad-hard GBT protocol. Results of the signal integrity, eye diagram analysis, path delays, and measurements of resource utilisation are presented which are figure of merit for efficient system performance.