Analysis and Comparison of Reduced Switch Topologies of Multilevel Inverter Using Various PWM Techniques

Recently, multilevel inverters have turned out to be common because of their ability in voltage activity and capacity. The multilevel inverter acquires near sinusoidal output from numerous dc voltage sources by utilizing a switching frequency. In this paper, a case study has been done with some newly recommended multilevel inverter (MLI) topologies with reduced number of power switches. An attempt has been made to compare them using various SPWM methods. Comparison and analysis is shown on the basis of total harmonic distortion (THD) with PD, POD, APOD applied to various topologies of seven-level inverter. As the proposed topologies have been suggested by different researchers for different applications, each configuration has its own benefits and limitations. Further, a compromise has to be made between number of switch count, complex modulation strategy and power quality.