Design & Modeling of Input Output Functionalities of FPGA based IO Block

As a part of my ongoing research towards Development of next generation High speed I/O&in continuation with the 2 technical survey papers already published by me I am bringing this research experiment paper covering - basic I/O concepts, functions, improvements, challenges found in the existing I/O, synchronization issues, open issues, case studies of Xilinx IO block. I have proposed a novel architecture to implement critical High speed I/O functions. I made designs for Digital modules, coded in Verilog & simulated in Xilinx ISE 14.5 to verify the functionality.