Performance Analysis of Cache Size and Set-Associativity using simpleScalar Benchmark

The ever growing space between the high-speed processor and slower main memory has always remained a performance bottleneck. Attempts have been made to address this challenge through the advent of smarter memories, an improved memory hierarchy, and deployment of high speed bus controllers. Another important dimension is to add cache units to the processor in order to benefit from the temporal and spatial, and even instruction locality and therefore, reduce the processormemory gap that ultimately results in a performance boost. In this paper, we demonstrate that increasing the cache size in order to reduce the capacity based misses results in further optimizing the performance. This results in increasing the associativity and block size and thus, reduce the conflict and compulsory based misses. We discuss the cache parameters set to achieve the minimum miss rate for the simpleScaler suite including Rijndael, Sha, Compress, Go, and Dijkstra benchmarks. Explicitly, we reduce the miss rate by using different cache configurations such as increasing the cache size, altering the block size, and varying the associativity. Notably, we achieve a minimal possible miss rate for the Rijndael benchmark, which is 10⁴. The results show the validity of an n size cache and x associativity, which is equal to an n/2 cache size and 2x associativity – 2: 1 cache rule of thumb.