Estimation and Interruption of Short Circuit Currents in HVDC Systems

A proper design of protection strategies in DC systems is challenging. Due to low line impedance, the short circuit current (SCC) increases rapidly to values higher than the DC converter ampacity, endangering the semiconductors. Different interruption schemes have been developed in the last years, using power semiconductor breakers or power converter with fault clearing capability at the terminal. This paper aims to describe and compare the existing solutions for SCC interruption in HVDC systems, introducing also analytical fault current estimation to accelerate the protection design. It ensures reliable identification of critical points and optimal protection design with reduced computational effort compared to EMT-simulations under a large number of grid parameters.