Research and Implementation of XDMA High Speed Data Transmission IP Core Based on PCI Express and FPGA

As part of the hardware-based high-speed network encryption communication control card, this paper mainly discussed how to realize high-speed data transmission between the FPGA and PC by Scatter-Gather DMA based on PCI Express bus. Firstly, the characteristics and protocols of PCIE bus, as well as the principle and implementation method of SG DMA were analyzed in detail. Then, the XDMA IP core was configured and generated in Vivado. This IP core fully realized the functions of transaction layer, physical layer and data link layer of PCIE protocol. This paper completed a test platform based on Xilinx Kintex XC7k420T FPGA to read and written DDR3 through the PCIE. Moreover, the driver of XDMA was written based on the underlying PCI Express library provided by Ubuntu 16.04. From the test results, the transmission efficiency of 4.19 MBytes data was 78.09% and 64.14% in H2C and C2H channels. The maximum bandwidth of the FPGA board used in this test is 20GT/s. The bandwidth of H2C channel was 15.62 Gbps, and that of C2H channel was 12.83 Gbps.